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BIOS Memory Reference Code and Validation Tool Development Engineer

Company: INTEL
Location: Castro Valley
Posted on: September 19, 2022

Job Description:

Job Description The Memory and I/O Technologies Team, MIO is excited to announce an opportunity within the Intel Datacenter and AI Group. MIO works to define and validate DDR5 and LPDDR5 DRAM memory and I/O technologies for Intel and as such, we work with other teams to improve BIOS and Memory Reference Code to improve margins in the platform. The qualified candidate would collaborate with engineering teams in Intel and in the DRAM industry to develop the next generation of memory test tools, improve memory related parameters of BIOS and Memory Reference Code, evaluate DDR memory with Row Hammer software, and debug memory issues related to platform/firmware interaction. Our team members are passionate about growth, innovation, and collaboration and we are looking for individuals who want to learn and grow so we can best support our customers with the highest quality possible. If you have a growth mindset and thrive in an engineering environment, you could be a great fit for our team. On any given day in our labs, you would test DRAM memory on Intel's platforms using the latest in memory test software, collect data across platforms and memory technologies, assess results and collaborate with engineering teams to drive improvements. It will be necessary to continuously keep up to date on emerging DRAM test improvements and apply new learnings to improve internal test processes. You should possess excellent written and verbal communication skills and have a positive attitude. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a positive factor in identifying top candidates. Requirements listed may be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Minimum Requirements: The candidate must have a Bachelor's degree in Computer Science, Electrical/Electronic Engineering, Computer Engineering, or related field. Minimum Qualifications: 3 years of experience with C programming/data structures and/or algorithms, and/or Advanced Configuration and Power Interface/Advanced Source Language (ACPI/ASL). 3 years of experience with x86 Assembly coding, BIOS coding, and/or Python. 3 years of experience with DDR DRAM architecture and/or design, memory controller interface programming, microprocessor cache, CPU to memory addressing, and/or memory access distribution. Preferred qualifications: Master's degree in Computer Science, Electrical/Electronic Engineering, Computer Engineering, or related field with 5 years of industry experience in x86 Assembly coding, BIOS coding, and/or Python. Inside this Business Group The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies---spanning software, processors, storage, I/O, and networking solutions---that fuel cloud, communications, enterprise, and government data centers around the world. Other Locations US,OR,Hillsboro;US,CA,Santa Clara Covid Statement Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Keywords: INTEL, Castro Valley , BIOS Memory Reference Code and Validation Tool Development Engineer, Engineering , Castro Valley, California

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