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Soc Design Engineer

Company: INTEL
Location: Castro Valley
Posted on: January 21, 2023

Job Description:

Job Description Come join Intel's FPGA Business Unit (Programmable Solutions Group) as an ASIC/SoC Digital Design Engineer. We make outstanding DDR PHYs for a wide range of applications. As an ASIC design Engineer, you will be primarily involved in the micro-architecture and RTL coding of critical blocks that make our PHYs so amazing. This is a unique opportunity where you will get an exposure to all phases of the design development, from architecture definition to design and verification to silicon bring-up and characterization.Our team only works on cutting edge state-of-the-art technology. Our projects range from high-performance memories such as DDR5/DDR4/LPDDR5 to projects that drive die-disaggregation with Intel's Industry leading package technology (EMIB). You can participate in early product definition, micro-architecture, define testing, physical integration, and verification strategy, while working closely with CAD and PD teams to identify and address timing bottlenecks.There are plenty of opportunities in our team to further develop your skill sets and/or learn something completely new. Working for an FPGA company gives you a rare opportunity to get exposed to software modelling of hardware while still working as a pure ASIC design engineer. Our team also allows you to get exposed to mixed-signal high speed designs where you get to interact with world class Analog designers. Mixed-signal design is a skill set that every high speed PHY designer will need to have going forward. Qualifications Qualification:

  • Logic design and RTL coding skills using Verilog or System Verilog.
  • Experience with multi-clock domain designs.
  • Experience with writing synthesis and timing constraints and understanding timing reports.
  • Experience with DFT, scan insertion, Design for Debug.
  • Experience with Low power design techniques.
  • Capability to work comfortably with cross-functional teams.
  • Experience with Timing closure (Timing and Functional ECO's)Minimum Qualification:BS, MS or PhD in Electrical Engineering or equivalent with 8+ years of experience in digital logic designPreferred Qualification:
    • Proven experience with high-speed memory PHY design for DDR5/4, LPDDR5/4 etc. Inside this Business Group The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential. Covid Statement Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: Annual Salary Range for jobs which could be performed in US, California: $156,410.00-$250,410.00
      Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Keywords: INTEL, Castro Valley , Soc Design Engineer, Engineering , Castro Valley, California

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